Hybrid crystallographic surface orientation substrate having one or more soi regions and/or bulk semiconductor regions

ABSTRACT

A substrate for a semiconductor device is disclosed including, in one embodiment, a plurality of semiconductor-on-insulator (SOI) wafers bonded to one another in a single stack. A distal end of the stack includes a first SOI region with a first semiconductor layer having a thickness and a first surface orientation. A surface of the single stack may further include a non-SOI region and/or at least one second SOI region. The non-SOI region may include bulk silicon that extends through all of the insulator layers of the single stack and has a thickness different than that of the first silicon layer. Each second SOI region has a second semiconductor layer having a thickness different than that of the first semiconductor layer and/or a different surface orientation than the first surface orientation. The substrate thus allows formation of different devices on optimal substrate regions that may include different surface orientations and/or different thicknesses and/or different bulk or SOI structures.

REFERENCE TO PRIOR APPLICATIONS

This application is a Divisional application of co-pending U.S. patentapplication Ser. No. 11/164,345, filed on Nov. 18, 2005, which is herebyincorporated by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

The invention relates generally to semiconductor devices, and moreparticularly, to a substrate having hybrid crystallographic surfaceorientations in one or more semiconductor-on-insulator (SOI) regionsand/or non-SOI regions for supporting different semiconductor devices.

2. Background Art

Performance improvement of semiconductor devices is a never-endingendeavor for manufacturers of those devices. One challenge currentlyfaced by the semiconductor industry is implementing differentsemiconductor devices, e.g., memory and logic devices, on a single chipwhile maintaining process simplicity and transistor performance. Thesedevices are referred to as “system-on-chips” (SoC) because theelectronics for a complete, working product are contained on a singlechip. One approach that is currently employed to improve performance ofa SoC is to fabricate the different types of semiconductor devices onsilicon substrates having optimal surface orientations. As used herein,“surface orientation” refers to the crystallographic structure orperiodic arrangement of silicon atoms on the surface of a wafer.Different surface orientations are optimal for different semiconductordevices. For example, an n-type field effect transistor (nFET) can beoptimized by being generated on silicon having a <100> surfaceorientation, while a p-type FET (pFET) can be optimized by beinggenerated on silicon having a <110> surface orientation. In addition,memory devices and nFETs are typically optimized when generated onsemiconductor-on-insulator (SOI) substrates, while pFETs are typicallyoptimized when generated on bulk silicon substrates.

One approach to providing these substrates includes bonding twosubstrates having different surface orientations to one another, with aninsulative silicon dioxide (oxide) layer in between to form an SOIsubstrate. However, there is a need in the industry for both SOI andnon-SOI areas on a single substrate for specific applications. Theseapplications may include, for example, power devices or devices where athick silicon substrate allows for desired strain from features such asembedded silicon germanium (SiGe) or the like. It also may be desirableto have more than one thickness of silicon over the buried oxide.

In view of the foregoing, there is a need in the art for a substratehaving different surface orientations and different structure, e.g., SOIand non-SOI regions.

SUMMARY OF THE INVENTION

A substrate for a semiconductor device is disclosed including, in oneembodiment, a plurality of semiconductor-on-insulator (SOI) wafersbonded to one another in a single stack. A distal end of the stackincludes a first SOI region with a first semiconductor layer having athickness and a first surface orientation. A surface of the single stackmay further include a non-SOI region and/or at least one second SOIregion. The non-SOI region may include bulk silicon that extends throughall of the insulator layers of the single stack and has a thicknessdifferent than that of the first silicon layer. Each second SOI regionhas a second semiconductor layer having a thickness different than thatof the first semiconductor layer and/or a different surface orientationthan the first surface orientation. The substrate thus allows formationof different devices on optimal substrate regions that may includedifferent surface orientations and/or different thicknesses and/ordifferent bulk or SOI structures.

A first aspect of the invention provides a substrate for a semiconductordevice, the substrate comprising: a stack including: a firstsemiconductor-on-insulator (SOI) wafer having a first semiconductorlayer having a first surface orientation, a second semiconductor layerhaving a second surface orientation and a first insulator layertherebetween, at least one second semiconductor-on-insulator (SOI) waferhaving a third semiconductor layer having a third surface orientation, afourth semiconductor layer having a fourth surface orientation and asecond insulator layer therebetween, and an oxidized insulator layerbetween the first SOI wafer and one of the at least one second SOIwafer; and a distal end of the stack including a first SOI region of thefirst SOI wafer including the first semiconductor layer, and at leastone second region including one of the following: a bulk semiconductorregion extending through all insulator layers of the stack, the bulkregion having a different thickness than a thickness of the firstsemiconductor layer of the first SOI region, and a second SOI regionhaving at least one of a different semiconductor thickness than athickness of the first semiconductor layer and a different surfaceorientation than the first semiconductor layer, wherein at least one ofthe first, second, third and fourth surface orientations is differentthan the other surface orientations.

A second aspect of the invention provides a substrate for asemiconductor device, the substrate comprising: a plurality ofsemiconductor-on-insulator (SOI) wafers bonded to one another in asingle stack, wherein a distal end of the single stack includes a firstSOI region with a first semiconductor layer having a thickness and afirst surface orientation, and wherein a surface of the single stackincludes at least one of the following: a non-SOI region extendingthrough all of the insulator layers of the single stack, the non-SOIregion having a thickness different than the thickness of the firstsemiconductor layer, and at least one second SOI region having a secondsemiconductor layer having at least one of the following: a thicknessdifferent than the thickness of the first semiconductor layer and adifferent surface orientation than the first surface orientation.

A third aspect of the invention provides a method of forming asemiconductor substrate, the method comprising the steps of: providing afirst semiconductor-on-insulator (SOI) wafer; bonding a second SOI waferto the first SOI wafer; forming an opening through a distalsemiconductor surface of the bonded wafers, the opening extending toexpose one of the other semiconductor layers of the SOI wafers; formingan isolation in the opening; and re-growing a semiconductor material inthe opening, the semiconductor material having the same surfaceorientation as the exposed semiconductor layer.

The illustrative aspects of the present invention are designed to solvethe problems herein described and other problems not discussed, whichare discoverable by a skilled artisan.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of this invention will be more readilyunderstood from the following detailed description of the variousaspects of the invention taken in conjunction with the accompanyingdrawings that depict various embodiments of the invention, in which:

FIG. 1 shows one embodiment of a substrate according to the invention.

FIG. 2 shows two SOI wafers.

FIG. 3 shows the two SOI wafers of FIG. 1 bonded together into a stack.

FIGS. 4-6 show steps of one embodiment of a method according to theinvention.

It is noted that the drawings of the invention are not to scale. Thedrawings are intended to depict only typical aspects of the invention,and therefore should not be considered as limiting the scope of theinvention. In the drawings, like numbering represents like elementsbetween the drawings.

DETAILED DESCRIPTION

Referring to FIG. 1, one embodiment of a substrate 100 for semiconductordevices according to the invention is illustrated. Substrate 100includes a plurality of semiconductor-on-insulator (SOI) wafers 102, 104bonded to one another in a single stack 106. While only two SOI wafers102, 104 are illustrated, as will be apparent to one with skill in theart, the teachings of the invention are not limited to just two SOIwafers. Each SOI wafer 102, 104 includes a semiconductor layer 122, 152(typically some form of silicon, silicon germanium or germanium), aninsulator layer 124, 154 (e.g., of silicon dioxide (SiO₂)), and asemiconductor layer (substrate) 126, 156, e.g., of bulk silicon. FirstSOI wafer 102 includes a first semiconductor layer 122 having a firstsurface orientation, a second semiconductor layer 126 having a secondsurface orientation and a first insulator layer 124 therebetween.Similarly, each second SOI wafer 104 includes a third semiconductorlayer 152 having a third surface orientation, a fourth semiconductorlayer 156 having a fourth surface orientation and a second insulatorlayer 154 therebetween. At least one semiconductor layer has a differentsurface orientation than the other layers. For example, as shown,semiconductor layer 126 has a different surface orientation. Each SOIwafer 102, 104 may be provided as a conventional SOI wafer, a separationby implantation of oxygen (SIMOX) wafer or a bonded wafer. At least onesemiconductor layer 122, 152, 126, 156 of stack 106 may include silicon,germanium, silicon germanium, strained silicon on silicon germanium orstrained silicon.

First and second SOI wafers 102, 104 are bonded together in any nowknown or later developed fashion. In one embodiment, bonding includesforming an oxidized insulator layer 128 on second SOI wafer 104, andjoining first SOI wafer 102. Each SOI wafer 102, 104 in stack 106 may besimilarly bonded to an adjacent SOI wafer by an oxidized insulatorlayer. In the illustrated embodiment, stack 106 includes two SOI wafers102, 104 so as to include three insulator layers 124, 154, 128 in thestack.

Substrate 100 also includes a surface 110 of a distal end 112 of singlestack 106 that includes a first SOI region 120 with a firstsemiconductor layer 122 having a thickness (T) and a first surfaceorientation. First SOI region 120 is formed as part of first SOI wafer102. As shown, the first surface orientation is <100>. However, anysurface orientation typically used for optimizing a particular devicemay be used, e.g., <100>, <110> or <111>. For example, nFETs prefer a<100> surface orientation for the highest mobility, while pFETs show thecorresponding mobility increase with a <110> surface orientation. In anyevent, as mentioned above, according to one embodiment of the invention,at least one of the surface orientations of silicon layers 122, 126,154, 156 is different than the other surface orientations.

Distal end 112 may further include a non-SOI region 130 and/or at leastone second SOI region 132, 134. Each region 130, 132, 134 may have adifferent silicon thickness than first SOI region 120. In addition, eachregion 130, 132, 134 may also have a surface orientation that is thesame as first SOI region 120 or different than first SOI region 120,depending on the surface orientation of the silicon layer from which theregion 130, 132, 134 is epitaxially grown. As a result, substrate 100may provide a variety of different surface orientations and/orsemiconductor thicknesses and/or structure, e.g., bulk or SOI, in asingle stack 106. Substrate 100, therefore, allows for formation of avariety of different devices on a single substrate 100.

Turning to the details of the illustrative regions, in one embodiment,non-SOI region 130 extends through all of insulator layers 124, 128, 154of single stack 106 to lowermost semiconductor layer (substrate) 156 andmay include bulk silicon. As a result, non-SOI region 130 has athickness (TB) different than the thickness (T) of first semiconductorlayer 122. In addition, as will be described below, since non-SOI region130 is epitaxially grown from semiconductor layer (substrate) 156, ithas the same surface orientation, which may be the same as the firstsurface orientation, e.g., <100>, or different. As illustrated, thesurface orientations are the same, i.e., <100>.

Each second SOI region 132, 134 may have a second semiconductor layer140, 142, respectively, having at least one of the following: athickness different than the thickness of first silicon layer 122 and adifferent surface orientation than the first surface orientation. Asillustrated, second SOI region 132 has a <110> surface orientation,while second SOI region 134 has a <100> surface orientation. Each secondSOI region 132, 134 has a different thickness than thickness (T) offirst semiconductor layer 122. The surface orientations and thickness ofsecond SOI regions 132, 134 can be determined based on from whichsemiconductor layer the region 132, 134 is epitaxially grown. In oneembodiment, as shown, first SOI region 120 has a <100> surfaceorientation, while second SOI region 132 has a <110> surfaceorientation, second SOI region 134 has a <100> surface orientation andnon-SOI region 130 has a <100> (shown) or a <110> surface orientation.However, if desired, distal end 112 may include three different surfaceorientations, e.g., first SOI region 120 with a <100> surfaceorientation, second SOI region 132 with a <110> surface orientation andnon-SOI region 130 and/or second SOI region 134 with a <111> surfaceorientation.

Each region 130, 132, 134 other than first SOI region 120 includes atrench isolation 162, e.g., of silicon dioxide (SiO₂).

Turning to FIGS. 2-6, one embodiment of a method of formingsemiconductor substrate 100 will now be described. It should berecognized that substrate 100 may be formed by a variety of othermethods not herein described, but considered within the scope of theinvention. Referring to FIGS. 2 and 3, in first steps, a first SOI wafer102 is provided, and then bonded to a second SOI wafer 104. As mentionedabove, the bonding step may include any now known or later developedmethod for bonding wafers. In one embodiment, as shown in FIG. 3, thebonding step may include forming an oxidized insulator layer 128 on asurface of second SOI wafer 104 and joining first and second SOI wafers102, 104 at oxidized insulator layer 128. It should be recognized,however, that various other bonding techniques now known or laterdeveloped are also possible, e.g., joining the first and second SOIwafers 102, 104 without an oxide insulating layer 128, which is referredto as silicon-to-silicon bonding.

As shown in FIG. 4, a next step includes forming an opening 180 througha distal semiconductor surface, i.e., silicon layer 122 of distal end112, of the bonded wafers. In one embodiment, opening 180 is formed bydepositing a mask 182, patterning mask 182 and etching 184, e.g.,reactive ion etching (RIE) using chemistry such as tetrafluoromethane(CF₄) or a polymerizing etch, to a selected depth in stack 106. That is,opening 180 extends to expose one of the other semiconductor layers 126,152, 156 of SOI wafers 102, 104. As illustrated, opening 180 exposessemiconductor layer 126. However, it could be any semiconductor layer.In addition, more than one opening 180 may be formed at any time, ifdesired. Mask 182 is then removed.

Next, as shown in FIG. 5, an isolation 160 is formed in opening 180 inany conventional manner for isolating the region from surroundingstructure during formation. In one embodiment, a first part of this stepincludes forming a sidewall spacer 160, which may include, for example,silicon dioxide (SiO₂) and/or silicon nitride (Si₃N₄). Sidewall spacers160 may have a thickness of, for example, 20-200 nm, depending on theneeds of the structure. As also shown in FIG. 5, a next step includesre-growing a semiconductor material 190 in opening 180. The growth maybe selective or non-selective depending on the masking scheme used.Growth is continued until the semiconductor material 190 reaches surface110, or may be planarized to meet surface 110 by chemical mechanicalpolishing (CMP). Semiconductor material 190, e.g., silicon, has the samesurface orientation as the exposed semiconductor layer, i.e., as shown,semiconductor layer 126.

As shown in FIG. 6, a second part of the isolation forming step mayinclude replacing each sidewall spacer 160 (FIG. 5) with a trenchisolation 162, e.g., silicon dioxide (SiO₂) and/or silicon nitride(Si₃N₄). The isolation step may be provided in other forms than thatdescribed, e.g., the isolations may be formed after semiconductormaterial re-growth. Trench isolations 162 allow for formation ofdifferent devices within each region and provide removal of thetypically defective epitaxial growth adjoining sidewall spacers 160,i.e., trenches etched for trench isolations 162 are wider than sidewallspacers 160.

It should be recognized that the above-described opening forming,isolation forming and re-growing steps may be repeated such thatnumerous regions 130, 132, 134 can be formed, as shown in FIG. 1. Forexample, the method may include the steps of forming another opening toa different semiconductor layer of SOI wafers 102, 104, and repeatingthe isolation forming and re-growing steps to form, for example, non-SOIregion 130 or another second SOI region 134. For non-SOI region 130,opening 180 would extend through all insulator layers 124, 128, 154 ofSOI wafers 102, 104 such that the re-grown semiconductor material wouldinclude the bulk silicon of layer 156. In any event, substrate 100 couldresult in at least one re-grown semiconductor material having a surfaceorientation different than a surface orientation of distal semiconductorlayer 122.

Traditional semiconductor processing would continue at this point,allowing the formation of certain devices on non-SOI regions 130 ofsubstrate 100, while other high performance devices could be formed onSOI regions 120, 132, 134 of multiple surface orientations or as partthe multiple crystals such as germanium (Ge) or silicon germanium(SiGe). That is, one of semiconductor layers 122, 126, 152, 156 couldoriginally include, for example, SiGe instead of silicon or silicongermanium on insulator instead of silicon-on-insulator. In an alternateembodiment, a SiGe layer could be deposited on a silicon substrate 156first, such that the dual buried oxide layers 128, 154 could be in SiGeand Si materials simultaneously. This structure would allow for thepossible growth of a strained silicon layer over the SiGe layer toprovide another combination of layers. It should be recognized thatvariations of this process can be made to the mask or etching depths toform slightly modified structures, and that these modifications areconsidered within the scope of the invention.

The foregoing description of various aspects of the invention has beenpresented for purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formdisclosed, and obviously, many modifications and variations arepossible. Such modifications and variations that may be apparent to aperson skilled in the art are intended to be included within the scopeof the invention as defined by the accompanying claims.

1. A method of forming a semiconductor substrate, the method comprisingthe steps of: providing a first semiconductor-on-insulator (SOI) wafer;bonding a second SOI wafer to the first SOI wafer; forming an openingthrough a distal semiconductor surface of the bonded wafers, the openingextending to expose one of the other semiconductor layers of the SOIwafers; forming an isolation in the opening; and re-growing asemiconductor material in the opening, the semiconductor material havingthe same surface orientation as the exposed semiconductor layer.
 2. Themethod of claim 1, wherein the opening extends through all insulatorlayers of the SOI wafers and the semiconductor material includes a bulksilicon.
 3. The method of claim 1, further comprising the step offorming another opening to a different semiconductor layer of the SOIwafers, and repeating the isolation forming and re-growing steps for theanother opening.
 4. The method of claim 3, wherein at least one re-grownsemiconductor material has a surface orientation different than asurface orientation of the distal semiconductor surface.
 5. The methodof claim 1, wherein the bonding step includes forming an oxidizedinsulator layer on a surface of the second SOI wafer and joining thefirst and second SOI wafers at the oxidized insulator layer.